As the name does not imply, it's NOT a portable console (despite the attributes) and it's NOT a Graphics Processing Unit (though it could). It's a pun derived from the GPL concept study, from which it reuses most of the ideas.
F-GPU is actually a self-contained development environment, with both hardware and software features that help design code for F-CPU (or YASEP or others). It can be considered as a reference design that can easily evolve, through additions or changes, into more specific products and application.
F-CPU is implemented on a small extension board, most likely inside a FPGA, with ample SDRAM and fast I/O (HDMI, 1000BaseT, SATA…)
This extension board is fitted on a base board, or “host board” that provides many slower interfaces :
The YASEP would be the embedded host processor, inside a FPGA : either a AFS600-PQ208 (13K LUT3, 24*512B SRAM, 512KiB program Flash, RTC, 12-bits AD,…) or M2GL005/M2GL010-TQ144 (6/12K LUT4, 64KiB SRAM, 128/256KiB Flash, 18-bits MACs,…). An external SSRAM chip is also considered (256K*16 bits).
The host processor implements a HTTP server (and HTTaP as well) to handle the setup, programming, flashing, debug, verification etc. of the guest processor. Most of the necessary software is stored by the guest processor, so the Web-based interface is independent from the user's host computer (as long as it has an Ethernet interface and can run a HTML5-capable web browser). There is no need of a vendor-specific JTAG probe or an OS-specific program (except for generating FPGA configuration bitstreams).
The guest processor (F-CPU or other) is likely to be implemented inside a M2S050 Flash-based FPGA (56K LUT4, 72 MAC, 256KiB Flash for code, 64KiB SRAM, CAN, Ethernet, USB, 69*2KiB SRAM blocks, 2x 36bits DDR controllers, 8 SERDES…). The FPGA is soldered on a module (similar to Emcraft's SoM) so a different FPGA family may be used without a total redesign of the PCB.
There could be a choice of the quantity of soldered SDRAM chips, external Flash or even network/storage/video… It communicates with the host processor through a full duplex parallel interface with FIFOs, so each processor can probe each other and send messages or blocks of data.
The whole F-GPU design can be extended to support multiple guest processors. The Host processor must be upgraded to a high-pincount FPGA. For example the M2S050 is available in 484 and 896 pins package, providing 267 or 377 I/O pins and 4 or 8 SERDES lanes. 4 or 8 host processors could be directly connected to the host FPGA, creating a heterogenous NUMA parallel computer.